Multicore RISC-V Processor

For my Computer Architecture class, ECE 4750, me and two partners, Andrew Tsai and Julia Ng, designed a multicore RISC-V CPU in SystemVerilog. For the first part of the project, we built an iterative multiplier that was capable of multiplying 32-bit signed integers. Next, we implemented a five-stage pipeline processor that incorporated the iterative multiplier and used aggressive bypassing. Then we designed a FSM cache that was two-way set associative with write-back, write-allocate, and LRU replacement policies. Finally, we instantiated four cores with four associated instruction caches and combined four data caches together in a banked configuration. We then connected the four cores with their respective instruction caches, the banked data cache, and a test memory to build a functional multicore CPU that we could use to run microbenchmarks written in C. At every step of the process, my partners and I relied on the PyMTL framework to verify our SystemVerilog designs. We focused on unit tests, directed tests, and random tests to verify things like bypass, stall, and squash logic and cache transactions. We also evaluated our design for the number of cycles various tasks took and qualitatively evaluated the cycle time, area, and energy at all stages of the design process. Overall, this project was a huge success and introduced me to developing in SystemVerilog and Pre-Silicon Verification practices. This project further inspired me to take additional courses in Computer Architecture like Advanced Computer Architecture, ECE 5750, and Complex Digital ASIC Design, ECE 5745.

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